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Shashikumar, D. R.
- Design of Finfet
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1 Department of ECE, Cambridge institute of Technology, Bangalore, Karnataka, IN
2 Cambridge Institute of Technology, Bangalore, Karnataka, IN
1 Department of ECE, Cambridge institute of Technology, Bangalore, Karnataka, IN
2 Cambridge Institute of Technology, Bangalore, Karnataka, IN
Source
International Journal of Engineering Research, Vol 5, No SP 5 (2016), Pagination: 1052-1057Abstract
Since the fabrication of MOSFET, the minimum channel length has been shrinking continuously. As devices shrink further and further, the problems with conventional (planar) MOSFETs are increasing. Industry is currently at the 90nm node (i.e., DRAM half metal pitch, which corresponds to gate lengths of about 70nm). As we go down to the 65nm, 45nm, 32NM, 22nm, 14nm etc., nodes, there seem to be no viable options of continuing forth with the conventional MOSFET. The motivation behind this decrease has been an increasing interest in high speed devices and in very large scale integrated circuits. The sustained scaling of conventional bulk device requires innovations to circumvent the barriers of fundamental physics constraining the conventional MOSFET device structure.- Image Processing System for Fertilization Management of Crops
Abstract Views :114 |
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Authors
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1 Dept. of CSE, Cambridge Institute of Technology, Bangalore, IN
1 Dept. of CSE, Cambridge Institute of Technology, Bangalore, IN